refactor F2aPipeline: reorder signals
@@ -11,8 +11,8 @@ class F2aPipeline(b: Int, fWidth: Int, qWidth: Int, aWidth: Int, addrWidth: Int)
val fMemQ = Input(Vec(b, UInt(fWidth.W)))
val qMemQ = Input(Vec(b, UInt(40.W)))
val amemWriteAddr = Input(UInt(addrWidth.W))
- val amemWrite = Output(Vec(b, WritePort(addrWidth, aWidth)))
val writeEnable = Input(Bool())
+ val amemWrite = Output(Vec(b, WritePort(addrWidth, aWidth)))
})
val quantizer = Module(new QuantizePipeline(b, fWidth, aWidth))
val addrBuf = RegNext(io.amemWriteAddr)
