Removing hard coded corners in openroad apr script
@@ -35,7 +35,7 @@ set sc_optmode [dict get $sc_cfg optmode]
set sc_process [dict get $sc_cfg pdk process]
set sc_mainlib [lindex [dict get $sc_cfg asic logiclib] 0]
set sc_targetlibs [dict get $sc_cfg asic logiclib]
-
+set sc_delaymodel [dict get $sc_cfg asic delaymodel]
set sc_stackup [dict get $sc_cfg asic stackup]
set sc_density [dict get $sc_cfg asic density]
set sc_hpinmetal [dict get $sc_cfg asic hpinlayer]
@@ -49,6 +49,7 @@ set sc_maxfanout [dict get $sc_cfg asic maxfanout]
set sc_maxlength [dict get $sc_cfg asic maxlength]
set sc_maxcap [dict get $sc_cfg asic maxcap]
set sc_maxslew [dict get $sc_cfg asic maxslew]
+set sc_scenarios [dict keys [dict get $sc_cfg mcmm]]
# PDK agnostic design rule translation
dict for {key value} [dict get $sc_cfg pdk grid $sc_stackup] {
@@ -89,10 +90,6 @@ set sc_endcap [dict get $sc_cfg library $sc_mainlib cells endcap]
# PDK Design Rules
set sc_techlef [dict get $sc_cfg pdk aprtech openroad $sc_stackup $sc_libtype lef]
-# TODO: workaround until OpenROAD allows floating-point 'tapmax' values.
-set sc_tapmax [expr {int([lindex [dict get $sc_cfg pdk tapmax] end])}]
-set sc_tapoffset [lindex [dict get $sc_cfg pdk tapoffset] end]
-
# TODO: why do we need to check whether key exists? I thought this was fixed.
if {[dict exists $sc_cfg suppy]} {
set sc_supplies [dict keys [dict get $sc_cfg supply]]
@@ -125,18 +122,18 @@ set sc_constraints [dict get $sc_cfg constraint]
# Read techlef
read_lef $sc_techlef
-# Read Targetlibs
-foreach lib $sc_targetlibs {
- read_liberty [dict get $sc_cfg library $lib nldm typical lib]
+# Read Libraries
+foreach item $sc_scenarios {
+ set libcorner [dict get $sc_cfg mcmm $item libcorner]
+ foreach lib "$sc_targetlibs $sc_macrolibs" {
+ #Lef
read_lef [dict get $sc_cfg library $lib lef $sc_stackup]
-}
-
-# Read Macrolibs
-foreach lib $sc_macrolibs {
+ #Liberty
if {[dict exists $sc_cfg library $lib nldm]} {
- read_liberty [dict get $sc_cfg library $lib nldm typical lib]
+ set lib_file [dict get $sc_cfg library $lib $sc_delaymodel $libcorner lib]
+ read_liberty $lib_file
+ }
}
- read_lef [dict get $sc_cfg library $lib lef $sc_stackup]
}
# Read Verilog
