Add error reporting to Netgen for checklist test
+import os
+
import siliconcompiler
from siliconcompiler.tools.netgen import count_lvs
@@ -63,7 +65,12 @@ def setup(chip):
else:
chip.add('tool', tool, 'input', step, index, f'{design}.vg')
- # TODO: add regex for errors
+ # Netgen doesn't have a standard error prefix that we can grep for, but it
+ # does print all errors to stderr, so we can redirect them to <step>.errors
+ # and use that file to count errors.
+ chip.set('tool', tool, 'stderr', step, index, 'suffix', 'errors')
+ chip.set('tool', tool, 'report', step, index, 'errors', f'{step}.errors')
+
chip.set('tool', tool, 'regex', step, index, 'warnings', '^Warning:', clobber=False)
report_path = f'reports/{design}.lvs.out'
@@ -91,9 +98,18 @@ def post_process(chip):
index = chip.get('arg', 'index')
design = chip.get('design')
+ with open(f'{step}.errors', 'r') as f:
+ errors = len(f.readlines())
+ chip.set('metric', step, index, 'errors', errors)
+
if step == 'lvs':
# Export metrics
- lvs_failures = count_lvs.count_LVS_failures(f'reports/{design}.lvs.json')
+ lvs_report = f'reports/{design}.lvs.json'
+ if not os.path.isfile(lvs_report):
+ chip.logger.warning('No LVS report generated. Netgen may have encountered errors.')
+ return
+
+ lvs_failures = count_lvs.count_LVS_failures(lvs_report)
# We don't count top-level pin mismatches as errors b/c we seem to get
# false positives for disconnected pins. Report them as warnings
