Active-HDL: Overwrite runsim.do instead of appending
The first line of runsim.do should use > rather than >> to overwrite
any existing contents of the file.
@@ -46,7 +46,7 @@ endif
# Create a DO script (Tcl-like but not fully compatible) based on the list of $(VERILOG_SOURCES)
$(SIM_BUILD)/runsim.do : $(VERILOG_SOURCES) $(VHDL_SOURCES) $(SIM_BUILD)
- @echo "alib $(RTL_LIBRARY)" >> $@
+ @echo "alib $(RTL_LIBRARY)" > $@
@echo "set worklib $(RTL_LIBRARY)" >> $@
ifneq ($(VHDL_SOURCES),)
@echo "acom $(ACOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES))" >> $@
