Add +acc to default VHDL compile options for Questa
This is required for regressions to pass and is already default for
Verilog compilation.
@@ -47,9 +47,11 @@ RTL_LIBRARY ?= work
TOPLEVEL := "$(RTL_LIBRARY).$(TOPLEVEL)"
ifndef VLOG_ARGS
- VLOG_ARGS = -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) -mfcu +acc
+ VLOG_ARGS = -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) -mfcu
endif
+COMPILE_ARGS += +acc
+
ifdef VERILOG_INCLUDE_DIRS
VLOG_ARGS += +incdir+$(VERILOG_INCLUDE_DIRS)
endif
