Cleanup adder example verilog
+// This file is public domain, it can be freely copied without restrictions.
+// SPDX-License-Identifier: CC0-1.0
// Adder DUT
-
`timescale 1ns/1ps
module adder #(
- parameter DATA_WIDTH = 4
+ parameter integer DATA_WIDTH = 4
) (
- input [DATA_WIDTH-1:0] A,
- input [DATA_WIDTH-1:0] B,
- output reg [DATA_WIDTH:0] X
+ input logic unsigned [DATA_WIDTH-1:0] A,
+ input logic unsigned [DATA_WIDTH-1:0] B,
+ output logic unsigned [DATA_WIDTH:0] X
);
- always @(A or B) begin
- X = A + B;
- end
+ assign X = A + B;
-`ifndef VERILATOR // traced differently
// Dump waves
initial begin
$dumpfile("dump.vcd");
$dumpvars(1, adder);
end
-`endif
endmodule
