Fix LR/SC sequence issue
@@ -228,7 +228,8 @@ class riscv_rand_instr_stream extends riscv_instr_stream;
function void randomize_instr(output riscv_instr instr,
input bit is_in_debug = 1'b0,
- input bit disable_dist = 1'b0);
+ input bit disable_dist = 1'b0,
+ input riscv_instr_group_t include_group[$] = {});
riscv_instr_name_t exclude_instr[];
if ((SP inside {reserved_rd, cfg.reserved_regs}) ||
((avail_regs.size() > 0) && !(SP inside {avail_regs}))) begin
@@ -244,7 +245,8 @@ class riscv_rand_instr_stream extends riscv_instr_stream;
end
end
instr = riscv_instr::get_rand_instr(.include_instr(allowed_instr),
- .exclude_instr(exclude_instr));
+ .exclude_instr(exclude_instr),
+ .include_group(include_group));
instr.m_cfg = cfg;
randomize_gpr(instr);
endfunction
