Add optional 'tool' parameter to Floorplan()
Now that we've split up PDK tech information by tool, this parameter
lets a designer specify which tool will consume the floorplan, so that
the floorplan is generated using the correctly-associated tech
information. The default is OpenROAD, maintaining API compatibility.
@@ -75,12 +75,12 @@ def _wire_to_rect(wire):
return (left, bottom, right, top)
-def _get_tech_lef_data(chip):
+def _get_tech_lef_data(chip, tool):
stackup = chip.get('asic', 'stackup')
libname = chip.get('asic', 'targetlib')[0]
libtype = chip.get('library', libname, 'arch')
- tech_lef = chip.find_files('pdk', 'aprtech', 'openroad', stackup, libtype, 'lef')[0]
+ tech_lef = chip.find_files('pdk', 'aprtech', tool, stackup, libtype, 'lef')[0]
return leflib.parse(tech_lef)
def _get_stdcell_info(chip, tech_lef_data):
@@ -148,7 +148,7 @@ class Floorplan:
stdcell_height (float): Height of standard cells in microns.
'''
- def __init__(self, chip):
+ def __init__(self, chip, tool='openroad'):
self.chip = chip
self.design = chip.get('design')
@@ -214,7 +214,7 @@ class Floorplan:
logging.warning(f'Macro {name} missing size in LEF, not adding '
'to available cells.')
- tech_lef_data = _get_tech_lef_data(chip)
+ tech_lef_data = _get_tech_lef_data(chip, tool)
stdcell_info = _get_stdcell_info(chip, tech_lef_data)
self.stdcell_name, self.stdcell_width, self.stdcell_height = stdcell_info
@@ -1406,7 +1406,7 @@ def _infer_diearea(chip):
chip.error = 1
return None
- lef_data = _get_tech_lef_data(chip)
+ lef_data = _get_tech_lef_data(chip, 'openroad')
_, _, lib_height = _get_stdcell_info(chip, lef_data)
core_width, core_height = _calculate_core_dimensions(density,
