Get target library only in ASIC synth flow
This configuration field is empty for FPGA targets
@@ -14,14 +14,10 @@ if {[dict get $sc_cfg flow $step copy] eq True} {
}
set topmodule [dict get $sc_cfg design]
-set target_lib [dict get $sc_cfg target_lib]
set mode [dict get $sc_cfg mode]
set target [dict get $sc_cfg target]
-#TODO: fix to handle multiple libraries
-set library_file [dict get $sc_cfg stdcell $target_lib model typical nldm lib]
-
#Inputs
set input_verilog "inputs/$topmodule.v"
set input_def "inputs/$topmodule.def"
@@ -30,6 +26,10 @@ set input_sdc "inputs/$topmodule.sdc"
yosys read_verilog $input_verilog
if {$mode eq "asic"} {
+ set target_lib [dict get $sc_cfg target_lib]
+ #TODO: fix to handle multiple libraries
+ set library_file [dict get $sc_cfg stdcell $target_lib model typical nldm lib]
+
#Outputs
set output_verilog "outputs/$topmodule.v"
set output_def "outputs/$topmodule.def"
