f4pga/common_modules/synth: use pathlib instead of os.path
#
# SPDX-License-Identifier: Apache-2.0
-import os
+from os import environ
from pathlib import Path
from f4pga.common import decompose_depname, get_verbosity_level, sub as common_sub
@@ -44,7 +44,7 @@ def yosys_synth(tcl, tcl_env, verilog_files=[], read_verilog_args=None, log=None
optional = []
if log:
optional += ['-l', log]
- env = os.environ.copy()
+ env = environ.copy()
env.update(tcl_env)
tcl = f'tcl {tcl}'
@@ -63,7 +63,7 @@ def yosys_synth(tcl, tcl_env, verilog_files=[], read_verilog_args=None, log=None
def yosys_conv(tcl, tcl_env, synth_json):
# Set up environment for TCL weirdness
- env = os.environ.copy()
+ env = environ.copy()
env.update(tcl_env)
return common_sub('yosys', '-p', f'read_json {synth_json}; tcl {tcl}', env=env)
@@ -76,13 +76,13 @@ class SynthModule(Module):
top = ctx.values.top
if ctx.takes.build_dir:
- top = os.path.join(ctx.takes.build_dir, top)
+ top = str(Path(ctx.takes.build_dir) / top)
mapping['eblif'] = top + '.eblif'
mapping['fasm_extra'] = top + '_fasm_extra.fasm'
mapping['json'] = top + '.json'
mapping['synth_json'] = top + '_io.json'
- b_path = os.path.dirname(top)
+ b_path = Path(top).parent.name
for extra in self.extra_products:
name, spec = decompose_depname(extra)
@@ -92,9 +92,7 @@ class SynthModule(Module):
f'(?) specifier. Product causing this error: `{extra}`.'
)
elif spec == 'req':
- mapping[name] = \
- os.path.join(b_path,
- ctx.values.device + '_' + name + '.' + name)
+ mapping[name] = str(Path(b_path) / f'{ctx.values.device}_{name}.{name}')
return mapping
@@ -117,9 +115,9 @@ class SynthModule(Module):
common_sub('python3', str(split_inouts), '-i', ctx.outputs.json, '-o',
ctx.outputs.synth_json)
- if not os.path.isfile(ctx.produces.fasm_extra):
- with open(ctx.produces.fasm_extra, 'w') as f:
- f.write('')
+ if not Path(ctx.produces.fasm_extra).is_file():
+ with Path(ctx.produces.fasm_extra).open('w') as wfptr:
+ wfptr.write('')
yield f'Converting...'
yosys_conv(str(conv_tcl), tcl_env, ctx.outputs.synth_json)
