Added error handler,
@@ -84,6 +84,9 @@ endif
$(SIM_BUILD)/runsim.do : $(VHDL_SOURCES) $(VERILOG_SOURCES) $(CUSTOM_SIM_DEPS) $(SIM_BUILD)
@echo "# Autogenerated file" > $@
+ @echo "onerror {" >> $@
+ @echo " quit -f -code 1" >> $@
+ @echo "}" >> $@
@echo "if [file exists $(RTL_LIBRARY)] {vdel -lib $(RTL_LIBRARY) -all}" > $@
@echo "vlib $(RTL_LIBRARY)" >> $@
@echo "vmap -c" >> $@
