Adding switch for to schema for design parameter override
Turns out to be a very useful feature for design space exploration!
Supported by Yosys/verilator
@@ -3150,6 +3150,26 @@ def schema_design(cfg):
"""
}
+ cfg['param'] = {
+ 'switch': '-p',
+ 'type': 'str',
+ 'lock': 'false',
+ 'requirement': 'optional',
+ 'defvalue': [],
+ 'short_help': 'Design Parameter Override',
+ 'param_help': "param <str>",
+ 'example': ["cli: -p 'N=64'",
+ "api: chip.add('param','N=64')"],
+ 'help': """
+ Overrides the given parameter of the top level module. The value
+ is limited to basic data literals. The parameter override is
+ passed into tools such as Verilator and Yosys. The parameters
+ support Verilog integer literals (64'h4, 2'b0, 4) and strings.
+ Strings must be supplied as properyl escaped double quotes
+ (eg. -p 'TYPE=\"FAST\"').
+ """
+ }
+
cfg['define'] = {
'switch': '-D',
'type': 'str',
