Handle macro libs in Yosys synthesis script
@@ -30,6 +30,8 @@ yosys read_verilog -sv $input_verilog
if {$mode eq "asic"} {
set targetlib [dict get $sc_cfg asic targetlib]
#TODO: fix to handle multiple libraries
+ # (note that ABC and dfflibmap can only accept one library from Yosys, so
+ # for now everything needs to be concatenated into one library regardless)
if {$target eq "skywater130"} {
# TODO: hack, we use separate synth library for Skywater
set library_file [dict get $sc_cfg stdcell $targetlib model typical nldm lib_synth]
@@ -37,6 +39,21 @@ if {$mode eq "asic"} {
set library_file [dict get $sc_cfg stdcell $targetlib model typical nldm lib]
}
+ if {[dict exists $sc_cfg asic macrolib]} {
+ set sc_macrolibs [dict get $sc_cfg asic macrolib]
+ } else {
+ set sc_macrolibs ""
+ }
+
+ # Read macro library files, and gather argument list to pass into stat later
+ # on (for area estimation).
+ set stat_libs ""
+ foreach libname $sc_macrolibs {
+ set macro_lib [dict get $sc_cfg macro $libname model typical nldm lib]
+ yosys read_liberty -lib $macro_lib
+ append stat_libs "-liberty $macro_lib"
+ }
+
#Outputs
set output_verilog "outputs/$topmodule.v"
set output_def "outputs/$topmodule.def"
@@ -61,7 +78,7 @@ if {$mode eq "asic"} {
yosys abc -liberty $library_file
- yosys stat -liberty $library_file
+ yosys stat -liberty $library_file {*}$stat_libs
########################################################
# Cleanup
