Write a complete synthesis flow based on default synthesis script
+# This script has been written based on the yosys's default synthesis script and the synthesis script in vtr-verilog-to-routing/vtr_flow/misc/yosyslib/synthesis.ys
+begin:
+ hierarchy -check -auto-top -purge_lib -libdir {{ lib_dir }}
+coarse:
proc
+ flatten
opt_expr
opt_clean
check
@@ -10,34 +15,41 @@ opt
wreduce
peepopt
opt_clean
-share
-opt
-memory -nomap
-opt -full
-
techmap -map +/adff2dff.v
techmap -map {{ lib_dir }}/adffe2dff.v
techmap -map {{ lib_dir }}/yosys_models.v */t:$mul */t:$mem */t:$sub */t:$add
-memory_map
-techmap
read_verilog -lib {{ lib_dir }}/adder.v
read_verilog -lib {{ lib_dir }}/multiply.v
read_verilog -lib {{ lib_dir }}/single_port_ram.v
read_verilog -lib {{ lib_dir }}/dual_port_ram.v
read_verilog {{ lib_dir }}/spram_rename.v
read_verilog {{ lib_dir }}/dpram_rename.v
-
-abc -lut {{ max_lut_size }}
-
-#Flatten the design
+ alumacc
+ share
+ opt
+ memory -nomap
+ opt_clean
+fine:
+ opt -fast -full
+ memory_map
+ opt -full
+ techmap
+ clean; opt_lut
+ flowmap -maxlut {{ max_lut_size }}
+ opt -fast
+ abc -fast
+ abc -fast -lut {{ max_lut_size }}
+ opt -fast
flatten
dffunmap
-opt -fast -noff
- # Check
+check:
+ hierarchy -check -purge_lib
stat
-#hierarchy -check -purge_lib
-#synth -run check
-
-# Clean and output blifver
+ check
+clean and output blif:
write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ
opt_clean -purge
+
+
+
+
