Fix documentation on how relative paths are resolved
@@ -288,17 +288,17 @@ The following variables are makefile variables, not environment variables.
.. make:var:: VERILOG_SOURCES
A list of the Verilog source files to include.
- Paths can be absolute or relative; if relative, they are interpreted as relative to the Makefile's location.
+ Paths can be absolute or relative; if relative, they are interpreted as relative to the location where ``make`` was invoked.
.. make:var:: VERILOG_INCLUDE_DIRS
A list of the Verilog directories to search for include files.
- Paths can be absolute or relative; if relative, they are interpreted as relative to the Makefile's location.
+ Paths can be absolute or relative; if relative, they are interpreted as relative to the location where ``make`` was invoked.
.. make:var:: VHDL_SOURCES
A list of the VHDL source files to include.
- Paths can be absolute or relative; if relative, they are interpreted as relative to the Makefile's location.
+ Paths can be absolute or relative; if relative, they are interpreted as relative to the location where ``make`` was invoked.
.. make:var:: VHDL_SOURCES_<lib>
@@ -375,7 +375,7 @@ The following variables are makefile variables, not environment variables.
.. make:var:: SIM_BUILD
- Use to define a scratch directory for use by the simulator. The path is relative to the Makefile location.
+ Use to define a scratch directory for use by the simulator. The path is relative to the location where ``make`` was invoked.
If not provided, the default scratch directory is :file:`sim_build`.
.. envvar:: SCRIPT_FILE
