Creating generic opensource fpga flow
Use partname to try to detect the vendor tool to use
I actually think this will work pretty well!! For things like ice that have multiple possibilities, you can always have a lattice flow.
import importlib
import os
import siliconcompiler
+import re
####################################################
# Flowgraph Setup
####################################################
-def setup_flow(chip, name=None):
-
-
- #Get edaflow, partname
- edaflow = chip.get('fpga','edaflow')[-1]
- partname = chip.get('fpga','partname')[-1]
-
- # Vendor/EDA lookup table
- if edaflow == 'xilinx':
- vendor_tool = 'vivado'
- elif edaflow == 'intel':
- vendor_tool = 'quartus'
- elif edaflow == 'lattice':
- vendor_tool = 'radiant'
- elif edaflow == 'microchip':
- vendor_tool = 'libero'
+def setup_flow(chip, partname):
# A simple linear flow
flowpipe = ['import',
'syn',
'apr',
- 'bitgen',
- 'program']
+ 'bitstream']
+
+ #TODO: add 'program' stage
for i in range(len(flowpipe)-1):
chip.add('flowgraph', flowpipe[i], 'output', flowpipe[i+1])
@@ -37,35 +24,24 @@ def setup_flow(chip, name=None):
if step == 'import':
tool = 'verilator'
elif step == 'syn':
- if edaflow in ['openfpga', 'icestorm']:
tool = 'yosys'
- else:
- tool = vendor_tool
elif step == 'apr':
- if edaflow in ['icestorm']:
+ if re.match('ice', partname):
tool = 'nextpnr'
- elif edaflow in ['openfpga']:
- tool = 'vpr'
else:
- tool = vendor_tool
- elif step == 'bitgen':
- if edaflow in ['icestorm']:
+ tool = 'vpr'
+ elif step == 'bitstream':
+ if re.match('ice', partname):
tool = 'icepack'
- elif edaflow in ['openfpga']:
- tool = 'openfpga'
else:
- tool = vendor_tool
+ tool = 'openfpga'
elif step == 'program':
- if edaflow in ['icestorm']:
- tool = 'FAIL'
- elif edaflow in ['openfpga']:
- tool = 'FAIL'
+ if re.match('ice', partname):
+ tool = 'iceprog'
else:
- tool = vendor_tool
-
+ tool = 'openfpga'
chip.set('flowgraph', step, 'tool', tool)
-
##################################################
if __name__ == "__main__":
@@ -76,7 +52,7 @@ if __name__ == "__main__":
# create a chip instance
chip = siliconcompiler.Chip(defaults=False)
# load configuration
- setup_flow(chip)
+ setup_flow(chip, "partname")
# write out results
chip.writecfg(output)
chip.write_flowgraph(prefix + ".svg")
