Fix target order in test_lock()
@@ -12,7 +12,7 @@ def test_lock():
# Create instance of Chip class
chip = siliconcompiler.Chip()
- chip.target("freepdk45_asicflow")
+ chip.target('asicflow_freepdk45')
chip.set('design', "gcd")
chip.set('design', "true", field="lock")
chip.set('design', "FAIL")
