make yosys use correct sdc
@@ -466,8 +466,8 @@ def get_abc_period(chip):
# get clock information from sdc files
# TODO: fix for fpga/asic differentiation later
- if chip.valid('input', 'asic', 'sdc'):
- for sdc in chip.find_files('input', 'asic', 'sdc'):
+ if chip.valid('input', 'constraint', 'sdc'):
+ for sdc in chip.find_files('input', 'constraint', 'sdc'):
lines = []
with open(sdc, 'r') as f:
lines = f.read().splitlines()
