New graph pipeline test
@@ -7,9 +7,40 @@ def test_graph():
chip = siliconcompiler.Chip()
chip.load_target('skywater130_demo')
- chip.graph("top","asicflow", prefix="a_")
- chip.graph("top","signoffflow", prefix="b_")
- chip.edge("top", "a_export", "b_import")
+ #RTL
+ chip.pipeline('rtl', [{'import' : 'surelog'},
+ {'syn' : 'yosys'},
+ {'export' : 'nop'},])
+
+ #APR
+ chip.pipeline('apr', [{'import' : 'nop'},
+ {'floorplan' : 'openroad'},
+ {'physyn' : 'openroad'},
+ {'place' : 'openroad'},
+ {'cts' : 'openroad'},
+ {'route' : 'openroad'},
+ {'dfm' : 'openroad'},
+ {'export' : 'klayout'}])
+
+ #SIGNOFF
+ chip.node('signoff', 'import', 'nop')
+ chip.node('signoff', 'extspice', 'magic')
+ chip.node('signoff', 'drc', 'magic')
+ chip.node('signoff', 'lvs', 'netgen')
+ chip.node('signoff', 'export', 'join')
+
+ chip.edge('signoff', 'import', 'drc')
+ chip.edge('signoff', 'import', 'extspice')
+ chip.edge('signoff', 'extspice', 'lvs')
+ chip.edge('signoff', 'lvs', 'export')
+ chip.edge('signoff', 'drc', 'export')
+
+ #TOP
+ chip.graph("top","rtl", name="rtl")
+ chip.graph("top","apr", name="apr")
+ chip.graph("top","signoff", name="dv")
+ chip.edge("top", "rtl", "apr")
+ chip.edge("top", "apr", "dv")
chip.write_flowgraph("top.png", flow="top")
