Update OpenROAD tool file to reduce requirements for new flows
@@ -78,7 +78,8 @@ def setup(chip, mode='batch'):
chip.set('tool', tool, 'threads', step, index, threads, clobber=clobber)
- # Input/Output requirements
+ # Input/Output requirements for default asicflow
+ if chip.get('option', 'flow') == 'asicflow':
if step == 'floorplan':
if (not chip.valid('input', 'netlist') or
not chip.get('input', 'netlist')):
@@ -215,6 +216,8 @@ def post_process(chip):
#Check log file for errors and statistics
step = chip.get('arg', 'step')
index = chip.get('arg', 'index')
+ flow = chip.get('option', 'flow')
+ tool = 'openroad'
logfile = f"{step}.log"
# parsing log file
@@ -244,6 +247,9 @@ def post_process(chip):
#TODO: not sure the openroad utilization makes sense?
cellarea = round(float(area.group(1)), 2)
utilization = round(float(area.group(2)), 2)
+ if utilization == 0:
+ totalarea = 0.0
+ else:
totalarea = round(cellarea/(utilization/100), 2)
chip.set('metric', step, index, 'cellarea', cellarea, clobber=True)
chip.set('metric', step, index, 'totalarea', totalarea, clobber=True)
@@ -253,7 +259,7 @@ def post_process(chip):
elif wns:
chip.set('metric', step, index, 'setupwns', round(float(wns.group(1)), 2), clobber=True)
elif slack:
- chip.set('metric', step, index, metric, round(float(slack.group(1)), 2), clobber=True)
+ chip.set('metric', step, index, 'setupslack', round(float(slack.group(1)), 2), clobber=True)
elif wirelength:
chip.set('metric', step, index, 'wirelength', round(float(wirelength.group(1)), 2), clobber=True)
elif vias:
@@ -271,9 +277,16 @@ def post_process(chip):
chip.set('metric', step, index, 'warnings', warnings, clobber=True)
#Temporary superhack!rm
- #Getting cell count and net number from DEF
- if errors == 0:
- with open("outputs/" + chip.design + ".def") as f:
+ #Getting cell count and net number from the first available DEF file output (if any)
+ out_def = ''
+ out_files = chip.get('tool', tool, 'output', step, index)
+ if out_files:
+ for fn in out_files:
+ if fn.endswith('.def'):
+ out_def = fn
+ break
+ if (errors == 0) and out_def:
+ with open(out_def) as f:
for line in f:
cells = re.search(r'^COMPONENTS (\d+)', line)
nets = re.search(r'^NETS (\d+)', line)
@@ -285,7 +298,7 @@ def post_process(chip):
elif pins:
chip.set('metric', step, index, 'pins', int(pins.group(1)), clobber=True)
- if step == 'sta':
+ if (flow == 'asicflow') and (step == 'sta'):
# Copy along GDS for verification steps that rely on it
shutil.copy(f'inputs/{chip.design}.gds', f'outputs/{chip.design}.gds')
