Moving constraints reading to happen after floor-plan load.
Not clear how this could pass our test suite? The SDC needs to be read after the design has beeen read in.
@@ -125,20 +125,6 @@ foreach lib $sc_macrolibs {
read_lef [dict get $sc_cfg library $lib lef]
}
-# Constraints
-if {[file exists "inputs/$sc_design.sdc"]} {
- # if file exists in flow, default to that
- read_sdc "inputs/$sc_design.sdc"
-} elseif {[llength $sc_constraints] > 0} {
- # otherwise, if we have user-provided constraints, read those
- foreach sdc $sc_constraints {
- read_sdc $sdc
- }
-} else {
- # fall back on default constraints file
- read_sdc "${sc_refdir}/sc_constraints.sdc"
-}
-
# Floorplan reads synthesis verilog, others read def
if {$sc_step == "floorplan"} {
# read synthesized verilog if it exists
@@ -161,6 +147,21 @@ if {$sc_step == "floorplan"} {
}
}
+# Constraints
+if {[file exists "inputs/$sc_design.sdc"]} {
+ # if file exists in flow, default to that
+ read_sdc "inputs/$sc_design.sdc"
+} elseif {[llength $sc_constraints] > 0} {
+ # otherwise, if we have user-provided constraints, read those
+ foreach sdc $sc_constraints {
+ read_sdc $sdc
+ }
+} else {
+ # fall back on default constraints file
+ read_sdc "${sc_refdir}/sc_constraints.sdc"
+}
+
+
###############################
# Common Setup
###############################
