add make_docs to syn_asic for now to make sure it builds docs
from siliconcompiler.tools.yosys.yosys import syn_setup, setup_asic, prepare_synthesis_libraries, create_abc_synthesis_constraints, syn_post_process
+import siliconcompiler
+
+def make_docs():
+ chip = siliconcompiler.Chip('<design>')
+ chip.load_target('freepdk45_demo')
+ chip.set('arg', 'step', '<step>')
+ chip.set('arg', 'index', '<index>')
+ chip.set('flowgraph', chip.get('option', 'flow'), '<step>', '<index>', 'tool', 'yosys')
+ chip.set('flowgraph', chip.get('option', 'flow'), '<step>', '<index>', 'task', 'syn_asic')
+ setup(chip)
+ return chip
def setup(chip):
''' Helper method for configs specific to ASIC synthesis tasks.
