Fixing asicflow test for new more restrictive set/add calls
@@ -14,15 +14,13 @@ def test_gcd_local_py():
gcd_ex_dir = gcd_ex_dir[:gcd_ex_dir.rfind('/tests/quick_tests/asic')] + '/examples/gcd/'
# Inserting value into configuration
+ chip.set('design', 'gcd')
+ chip.target("freepdk45_asicflow")
chip.add('source', gcd_ex_dir + 'gcd.v')
- chip.add('design', 'gcd')
- chip.add('clock', 'clock_name', 'pin', 'clk')
+ chip.set('clock', 'clock_name', 'pin', 'clk')
chip.add('constraint', gcd_ex_dir + 'gcd.sdc')
- chip.set('target', "freepdk45_asicflow")
chip.set('asic', 'diesize', "0 0 100.13 100.8")
chip.set('asic', 'coresize', "10.07 11.2 90.25 91")
- chip.set_jobid()
- chip.target()
chip.set('quiet', 'true')
chip.set('relax', 'true')
