Add dummy writes to status and ie CSRs
@@ -340,6 +340,7 @@ class riscv_asm_program_gen extends uvm_object;
init_floating_point_gpr();
end
core_is_initialized();
+ gen_dummy_csr_write();
endfunction
// Setup MISA based on supported extensions
@@ -384,6 +385,37 @@ class riscv_asm_program_gen extends uvm_object;
end
endfunction
+ // Generate some dummy writes to xSTATUS/xIE at the beginning of the test to check
+ // repeated writes to these CSRs.
+ virtual function void gen_dummy_csr_write();
+ string instr[$];
+ case (cfg.init_privileged_mode)
+ MACHINE_MODE: begin
+ instr.push_back($sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], MSTATUS));
+ instr.push_back($sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], MIE));
+ instr.push_back($sformatf("csrw 0x%0x, x%0d", MSTATUS, cfg.gpr[0]));
+ instr.push_back($sformatf("csrw 0x%0x, x%0d", MIE, cfg.gpr[1]));
+ end
+ SUPERVISOR_MODE: begin
+ instr.push_back($sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], SSTATUS));
+ instr.push_back($sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], SIE));
+ instr.push_back($sformatf("csrw 0x%0x, x%0d", SSTATUS, cfg.gpr[0]));
+ instr.push_back($sformatf("csrw 0x%0x, x%0d", SIE, cfg.gpr[1]));
+ end
+ USER_MODE: begin
+ instr.push_back($sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], USTATUS));
+ instr.push_back($sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], UIE));
+ instr.push_back($sformatf("csrw 0x%0x, x%0d", USTATUS, cfg.gpr[0]));
+ instr.push_back($sformatf("csrw 0x%0x, x%0d", UIE, cfg.gpr[1]));
+ end
+ default: begin
+ `uvm_fatal(`gfn, "Unsupported boot mode")
+ end
+ endcase
+ format_section(instr);
+ instr_stream = {instr_stream, instr};
+ endfunction
+
// Initialize general purpose registers with random value
virtual function void init_gpr();
string str;
