Docs: add note about relative paths in VERILOG/VHDL_SOURCES.
If the paths are relative, then they will be interpreted as relative
to the Makefile location (i.e. the file that they are defined in).
This may not be true for all simulators at the moment, in which case
that should be fixed.
@@ -58,10 +58,12 @@ and
.. make:var:: VERILOG_SOURCES
A list of the Verilog source files to include.
+ Paths can be absolute or relative; if relative, they are interpreted as relative to the Makefile's location.
.. make:var:: VHDL_SOURCES
A list of the VHDL source files to include.
+ Paths can be absolute or relative; if relative, they are interpreted as relative to the Makefile's location.
.. make:var:: VHDL_SOURCES_<lib>
