Clarify a note about Verilator support
* There's no need to describe the internal workings of Verilator in the
cocotb docs.
* We don't document for other simulators that they only support a single
language, so don't do that for Verilator either.
@@ -92,9 +92,7 @@ In order to use this simulator, set :make:var:`SIM` to ``verilator``:
make SIM=verilator
-Verilator converts Verilog code to C++ code that is compiled.
-It does not support VHDL.
-One major limitation compared to standard Verilog simulators is that it does not support delayed assignments.
+One major limitation compared to standard Verilog simulators is that it does not support delayed assignments when accessed from cocotb.
To run cocotb with Verilator, you need ``verilator`` in your PATH.
