Simplifying example, stopping after floorplan.
Simplest possible test case with SDC support and physical information
@@ -5,16 +5,13 @@ chip = siliconcompiler.Chip() # create chip object
# Technology setup
chip.target("freepdk45") # set up pdk
-# Create tasks
+# Create tasks flow graph
chip.node('import', 'surelog') # import task
chip.node('syn', 'yosys') # synthesis task
chip.node('floorplan', 'openroad') # floorplan task
-chip.node('physyn', 'openroad') # physical synthesis task
-
-# Connect tasks into a flow
-chip.edge('import', 'syn')
-chip.edge('syn', 'floorplan')
-chip.edge('floorplan', 'physyn')
+chip.edge('import', 'syn') # connect import-->syn
+chip.edge('syn', 'floorplan') # connect syn-->floorplan
+chip.write_flowgraph("add_syn.png")
# Design
chip.add('source','add.v') # load source files
@@ -25,6 +22,7 @@ chip.set('clock','clk','period',1.0) # define clock period of clock 'clk'
# Options
chip.set('quiet', True) # Redirect tool outputs to file
+
# Compile
chip.run() # run compilation
