iverilog: Set toplevel at build
When a file contains modules that wrap the toplevel module, iverilog
will not have the toplevel at its own toplevel, but only inside the
wrapper modules.
Therefore, explicitly pass the toplevel module at build to iverilog.
@@ -56,7 +56,7 @@ BUILD_VPI=1
# Compilation phase
$(SIM_BUILD)/sim.vvp: $(SIM_BUILD) $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS)
- $(CMD) -o $(SIM_BUILD)/sim.vvp -D COCOTB_SIM=1 $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
+ $(CMD) -o $(SIM_BUILD)/sim.vvp -D COCOTB_SIM=1 -s $(TOPLEVEL) $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
# Execution phase
