examples: aes correct setup
+#!/usr/bin/env python3
+
import os
import siliconcompiler
@@ -20,12 +22,12 @@ def rtl2gds(design='aes',
# FLOW OVERLOAD
rootdir = os.path.dirname(__file__)
if rtl is None:
- chip.add('source', os.path.join(rootdir, f"{design}.v"))
+ chip.add('input', 'verilog', os.path.join(rootdir, f"{design}.v"))
if sdc is None:
- chip.add('constraint', os.path.join(rootdir, f"{design}.sdc"))
+ chip.add('input', 'sdc', os.path.join(rootdir, f"{design}.sdc"))
- chip.set('relax', True)
- chip.set('quiet', True)
+ chip.set('option', 'relax', True)
+ chip.set('option', 'quiet', True)
chip.set('asic', 'diearea', [(0,0), (width,height)])
chip.set('asic', 'corearea', [(10,10), (width-10,height-10)])
