Simplifyng example to use a single clock
//#############################################################################
-//# Function: Generic Memory Example for SiliconCompiler Project #
+//# Function: Generic Memory Example #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT #
@@ -11,13 +11,12 @@ module hello_world # (parameter DW = 32, // memory width
parameter DUALPORT= 1, // limit dual port
parameter AW = $clog2(DEPTH) // address width
)
- (// read-port
- input rd_clk,// rd clock
+ (input clk, //single clock
+ // read-port
input rd_en, // memory access
input [AW-1:0] rd_addr, // address
output [DW-1:0] rd_dout, // data output
// write-port
- input wr_clk,// wr clock
input wr_en, // memory access
input [AW-1:0] wr_addr, // address
input [DW-1:0] wr_din // data input
@@ -38,7 +37,7 @@ module hello_world # (parameter DW = 32, // memory width
//write port
//#########################################
- always @(posedge wr_clk)
+ always @(posedge clk)
if (wr_en)
ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0];
@@ -50,7 +49,7 @@ module hello_world # (parameter DW = 32, // memory width
//Configurable output register
reg [DW-1:0] rd_reg;
- always @ (posedge rd_clk)
+ always @ (posedge clk)
if(rd_en)
rd_reg[DW-1:0] <= rdata[DW-1:0];
@@ -58,7 +57,8 @@ module hello_world # (parameter DW = 32, // memory width
assign rd_dout[DW-1:0] = (REG==1) ? rd_reg[DW-1:0] :
rdata[DW-1:0];
-endmodule // oh_ram
+endmodule // hello_world
+
