All linting fixes
One small bug fix on vlib, there should have been a copy entry instead of a tyoe (double bug)
import re
import os
-import textwrap
import sys
###############################################################################
@@ -91,10 +90,8 @@ def schema_istrue(value):
''' Checks schema boolean string and returns Python True/False
'''
boolean = value[-1].lower()
- if boolean == "true":
- return True
- else:
- return False
+ return bool(boolean == "true")
+
def schema_check(cfg, leafkey, value):
''' Checks that leaf cell value agrees with type
@@ -2326,7 +2323,6 @@ def schema_options(cfg):
}
cfg['quiet'] = {
- 'short_help' : 'Quiet Execution Option',
'switch': '-quiet',
'type': 'bool',
'lock': 'false',
@@ -3177,7 +3173,7 @@ def schema_design(cfg):
'switch': '-v',
'type': 'file',
'lock': 'false',
- 'type' : 'false',
+ 'copy': 'false',
'requirement': 'optional',
'defvalue': [],
'hash': [],
@@ -3507,7 +3503,7 @@ def schema_asic(cfg):
'defvalue': [],
'short_help': 'Design Maximum Net Capacitance',
'param_help': "asic maxcap <str>",
- 'example': ["cli: -asic_maxcap 0.25e-12",
+ 'example': ["cli: -asic_maxcap '0.25e-12'",
"api: chip.add('asic', 'maxcap', '0.25e-12')"],
'help': """
The maximum allowed capacitance per net. The number is specified
@@ -3523,7 +3519,7 @@ def schema_asic(cfg):
'defvalue': [],
'short_help': 'Design Maximum Net Slew',
'param_help': "asic maxslew <str>",
- 'example': ["cli: -asic_maxslew 01e-9",
+ 'example': ["cli: -asic_maxslew '01e-9'",
"api: chip.add('asic', 'maxslew', '1e-9')"],
'help': """
The maximum allowed capacitance per net. The number is specified
