Shortening simple example further
-import siliconcompiler
-
+import siliconcompiler # import python package
chip = siliconcompiler.Chip() # create chip object
-
-# Technology setup
-chip.target("freepdk45") # set up pdk
-
-# Create tasks flow graph
-chip.node('import', 'surelog') # import task
-chip.node('syn', 'yosys') # synthesis task
-chip.node('floorplan', 'openroad') # floorplan task
+chip.target("freepdk45") # load predefined target pdk
+chip.node('import', 'surelog') # create import task
+chip.node('syn', 'yosys') # create synthesis task
+chip.node('floorplan', 'openroad') # create floorplan task
chip.edge('import', 'syn') # connect import-->syn
chip.edge('syn', 'floorplan') # connect syn-->floorplan
-chip.write_flowgraph("add_syn.png")
-
-# Design
-chip.add('source','add.v') # load source files
+chip.add('source','add.v') # define list of source files
chip.set('design','add') # set top module
-chip.set('clock','clk','pin','clk') # bind pin 'clk' to clock name 'clk'
-chip.set('clock','clk','period',1.0) # define clock period of clock 'clk'
-
-# Options
-chip.set('quiet', True) # Redirect tool outputs to file
-
-
-# Compile
+chip.set('clock','clk','pin','clk') # bind pin 'clk' to clock named 'clk'
+chip.set('clock','clk','period',1.0) # define period of clock named 'clk'
+chip.set('quiet', True) # redirect tool output to log file
chip.run() # run compilation
-
-# Results
-chip.summary() # print summary
+chip.summary() # print results summary
