Fix constraint setup in gcd_chip to get tests to pass
This is actually hiding a bug in our new constraint reading, will fix and
add a proper test in a future PR.
@@ -9,7 +9,8 @@ def gcd_chip():
chip.target('asicflow_freepdk45')
chip.add('source', os.path.join(gcd_ex_dir, 'gcd.v'))
chip.set('clock', 'clock_name', 'pin', 'clk')
- chip.add('constraint', os.path.join(gcd_ex_dir, 'gcd.sdc'))
+ chip.set('clock', 'clock_name', 'period', 2)
+ chip.add('constraint', os.path.join(gcd_ex_dir, 'gcd_noclock.sdc'))
chip.set('asic', 'diearea', [(0,0), (100.13,100.8)])
chip.set('asic', 'corearea', [(10.07,11.2), (90.25,91)])
chip.set('quiet', 'true', clobber=True)
