Update fpga target
@@ -18,6 +18,9 @@ def setup_eda(chip, name=None):
for step in chip.cfg['steplist']['value']:
if step == 'import':
+ if chip.get('ir')[-1] == 'uhdm':
+ vendor = 'surelog'
+ elif chip.get('ir')[-1] == 'verilog':
vendor = 'verilator'
elif step == 'syn':
vendor = 'yosys'
