Fix a typo in riscvOVPsim
ovpsim can support b-ext now
# riscOVPsim configuration file converted from YAML
--variant RV32I
---override iscvOVPsim/cpu/add_Extensions=MCB
+--override riscvOVPsim/cpu/add_Extensions=MCB
--override riscvOVPsim/cpu/misa_MXL=1
--override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0
--override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0
