Fix hardcoded FPGA flows
The outer for loop seems to be a mistake - it resulted in each setup
function getting called multiple times.
@@ -53,14 +53,6 @@ def setup_target(chip):
chip.cfg['mode']['value'] = ['fpga']
- chip.cfg['design_flow']['value'] = ['import',
- 'syn',
- 'floorplan',
- 'place',
- 'route',
- 'export']
-
- for step in (['floorplan', 'place', 'route', 'export']):
if target == 'ice40' :
chip.cfg['design_flow']['value'] = ['import',
'syn',
@@ -77,7 +69,9 @@ def setup_target(chip):
'place',
'route',
'export']
-
+ setup_step(chip, 'import', 'verilator', 'verilator')
+ setup_step(chip, 'syn', 'yosys', 'yosys')
+ for step in (['floorplan', 'place', 'route', 'export']):
setup_step(chip, step, 'vpr', 'vpr')
else:
if os.getenv('SCPATH') == None:
