Fixed issue with automatic top module extraction
Not sure how this crept in there, may be time for a test suite...
@@ -780,6 +780,7 @@ class Chip:
subprocess.run(cmd, shell=True)
#hack: extracting topmodule from concatenated verilator files
modules = 0
+ if(len(self.cfg['design']['value']) < 1):
with open("verilator.v", "r") as open_file:
for line in open_file:
modmatch = re.match('^module\s+(\w+)', line)
@@ -793,6 +794,8 @@ class Chip:
else:
self.logger.info('Setting design (topmodule) to %s', topmodule)
self.cfg['design']['value'].append(topmodule)
+ else:
+ topmodule = self.cfg['design']['value'][-1]
cmd = "cp verilator.v " + "outputs/" + topmodule + ".v"
subprocess.run(cmd, shell=True)
