Propagate riviera return code, non-zero on error
Fixes
@@ -90,7 +90,11 @@ endif
# Create a TCL script based on the list of $(VERILOG_SOURCES)
$(SIM_BUILD)/runsim.tcl : $(VERILOG_SOURCES) $(VHDL_SOURCES) $(SIM_BUILD)
- echo "alib $(RTL_LIBRARY)" > $@
+ echo "onerror {" > $@
+ echo " puts [read [open sim.log r]]" >> $@
+ echo " quit -code 1" >> $@
+ echo "}" >> $@
+ echo "alib $(RTL_LIBRARY)" >> $@
echo "set worklib $(RTL_LIBRARY)" >> $@
ifneq ($(VHDL_SOURCES),)
echo "acom $(ACOM_ARGS) $(VHDL_SOURCES)" >> $@
@@ -141,7 +145,7 @@ endif
# Note it's the redirection of the output rather than the 'do' command
# that turns on batch mode (i.e. exit on completion/error)
results.xml: $(SIM_BUILD)/runsim.tcl $(COCOTB_LIBS) $(COCOTB_VHPI_LIB) $(COCOTB_VPI_LIB) $(CUSTOM_SIM_DEPS)
- cd $(SIM_BUILD) && PYTHONPATH=$(LIB_DIR):$(SIM_ROOT):$(PWD):$(NEW_PYTHONPATH) GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+ set -o pipefail; cd $(SIM_BUILD) && PYTHONPATH=$(LIB_DIR):$(SIM_ROOT):$(PWD):$(NEW_PYTHONPATH) GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
$(LIB_LOAD) MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) $(CMD) -do runsim.tcl | tee sim.log
clean::
