Update src/riscv_debug_rom_gen.sv
@@ -93,9 +93,11 @@ class riscv_debug_rom_gen extends riscv_asm_program_gen;
cfg.num_debug_sub_program);
main_program[hart].post_process_instr();
main_program[hart].generate_instr_stream(.no_label(1'b1));
- debug_main = {debug_main, main_program[hart].instr_string_list};
- // Jump to debug_end section (before the debug sub-routines)
- debug_main = {debug_main, $sformatf("%sj debug_end", indent)};
+ debug_main = {debug_main,
+ main_program[hart].instr_string_list,
+ $sformatf("%sla x%0d, debug_end", indent, cfg.scratch_reg),
+ $sformatf("%sjalr x0, x%0d, 0", indent, cfg.scratch_reg)
+ };
insert_sub_program(sub_program[hart], debug_main);
gen_section($sformatf("%0sdebug_rom", hart_prefix(hart)), debug_main);
if (cfg.enable_ebreak_in_debug_rom) begin
